The present invention relates generally to integrated circuits and, in particular, to a high speed voltage level shifter.
With the introduction of integrated circuits with geometry below 0.13 xcexcm, lower power supply voltages have become necessary to maintain device reliability. Consequently, supply voltage has decreased from 3.3 volts to 1.2 volts or less. However, many interface signals still use the logic level from 0 to 3.3 or 5 volts. The circuitry therefore can be divided into xe2x80x9ccorexe2x80x9d circuits and I/O circuits, where the core logic operates at the lower 1.2 volts, and the I/O circuits operate at 3.3 volts. To interface between circuits requiring different voltage levels, a voltage level shifter is employed to switch between the voltage levels of the respective circuits.
FIG. 1 shows a well-known circuit implementation of a voltage level shifter 100. A NMOS transistor MN1 has its gate connected to a core circuit supply voltage (VCCL). Both PMOS transistors MP1, MP2 have their sources connected to an I/O voltage source VCCH, which has a higher voltage potential than VCCL. The level shifter 100 translates a low voltage input signal at an input terminal 110 to a high voltage output signal at an output terminal 130. For such a voltage level shifter to operate properly, the PMOS transistor MP1 is xe2x80x9cweakxe2x80x9d compared to the transistors MN1, MN2 and MP2.
With continued reference to FIG. 1, when the input signal is logic low, the NMOS transistor MN2 is xe2x80x9conxe2x80x9d via an inverter 120. As a result, the NMOS transistor MN2 electrically drives the output terminal 130 to ground. Further, the logic low output signal turns xe2x80x9conxe2x80x9d the PMOS transistor MP1 which provides the supply voltage VCCH to a gate of the PMOS transistor MP2, thereby the PMOS transistor MP2 is held xe2x80x9coffxe2x80x9d.
When the input signal goes high, the NMOS transistor MN2 is turned xe2x80x9coffxe2x80x9d. The NMOS transistor MN1 electrically connects the gate of the PMOS transistor MP2 to an inverted input signal at logic low (i.e., ground). Hence, the PMOS transistor MP2 is turned xe2x80x9conxe2x80x9d and provides the supply voltage VCCH to the output terminal 130.
The voltage level shifter 100 is suitable for ordinary applications. However, when the supply voltage VCCL approaches 1.2 volts or less, the NMOS transistors in the level shifter 100 cannot be conducted sufficiently due to a typical threshold voltage of 0.8 volts. The gate voltage that brings about conduction in a transistor is called the threshold voltage. In the case of an input signal having a voltage swing between 0 and 1.2 volts, an output signal at the output terminal 130 should be logic low when the gate of the NMOS transistor MN2 is at 1.2 volts, e.g. logic high. Nevertheless, the NMOS transistor MN2 cannot be turned xe2x80x9conxe2x80x9d sufficiently since the voltage drop across the gate and source of the NMOS transistor MN2 is no more than 0.4 volts, which barely allows it to overcome the pull-up capability of the PMOS transistor MP2. As a result, the output signal is weakly pulled to ground by NMOS transistor MN2. Referring to FIG. 2, the input signal IN shown is a substantially square wave having a low voltage level of 0 and a high voltage level of 1.2 volts. The output signal OUT has a voltage swing between 0 and 3.3 volts. It can be seen that the output signal OUT is poor and suffers from relatively slow falling time. Such a defect is further exacerbated when the supply voltage VCCL for xe2x80x9ccorexe2x80x9d circuits is even lower. Hence, owing to its relative slowness the prior art level shifter 100 cannot be applied to high speed circuitry with xe2x80x9ccorexe2x80x9d circuits having a very low supply voltage.
Accordingly, what is needed is a high speed voltage level shifter that overcomes the disadvantages associated with the prior art.
It is an object of the present invention to provide a high speed voltage level shifter for use in circuitry having xe2x80x9ccorexe2x80x9d circuits which operate at a very low supply voltage.
The present invention is directed to a voltage level shifter including a boost circuit and a voltage shifting stage. The voltage level shifter also has an input terminal and an output terminal. The input terminal is used to receive a non-inverted input signal having a first voltage level and a second voltage level, in which the first voltage level is a reference voltage level and the second voltage level is higher than the first voltage level. The boost circuit receives the non-inverted input signal. According to the non-inverted input signal, the boosted circuit produces a boosted signal, where the boosted signal is at a third voltage level when the non-inverted input signal is at the first voltage level, and at the first voltage level when the non-inverted input signal is at the second voltage level. In particular, the third voltage level is higher than the second voltage level. The voltage shifting stage is coupled to the boost circuit. In response to an inverted input signal and the boosted signal, the voltage shifting stage produces an output signal at a fourth voltage level when the inverted input signal and the boosted signal are both at the first voltage level, and at the first voltage level when the inverted input signal is at the second voltage level and the boosted signal is at the third voltage level. Therefore, the output terminal is used to provide the output signal having an output voltage swing between the first voltage level and the fourth voltage level.
In a preferred embodiment, the boost circuit includes a capacitor for producing an intermediate signal at the third voltage level when the inverted input signal is at the second voltage level. The boost circuit also has a first P-type transistor, a second P-type transistor, and a first N-type transistor. In response to the inverted input signal, the first P-type transistor charges the capacitor when the inverted input signal is at the first voltage level. When the non-inverted input signal is at the second voltage level, the first N-type transistor pulls down the boosted signal to the first voltage level. The second P-type transistor passes the intermediate signal to the boosted signal when the non-inverted input signal is at the first voltage level. Further, the capacitor is charged, by way of the first P-type transistor, from a first power source having the second voltage level, such that the intermediate signal substantially remains at the second voltage level when the inverted input signal is at the first voltage level.